1. Field of the Invention
The present invention relates to an image display system implemented with a mirror device manufactured as a MEMS device to function as a spatial light modulator (SLM). More particularly this invention relates to a technique used to manufacture a mirror element includes a structural body having no border surface straddling a semiconductor material layer.
2. Description of the Related Art
Even though in recent years, there have been significant advances made in the technologies for implementing an electromechanical mirror device as a spatial light modulator (SLM), there are still limitations and difficulties when state of the art current technologies are applied to provide a high quality image. Specifically, when the images are digitally controlled, the image quality is adversely affected due to the limitation that the images are not displayed with sufficient number of gray scales.
An electromechanical mirror device is drawing a considerable interest and commonly employed as a spatial light modulator (SLM) in the image project apparatuses. The electromechanical mirror device is typically implemented with a “mirror array” comprising a large number of mirror elements. In general, the number of mirror elements may range from 60,000 to several millions of micromirror pieces are manufactured as two-dimensional array on a surface of a substrate in an electromechanical mirror device.
Referring to FIG. 1A for an image display system 1 disclosed in U.S. Pat. No. 5,214,420 that comprises a screen 2. The display system 1 further includes a light source 10 to project an illumination light for displaying images on the screen 2. The illumination light 9 from the light source is further focused and directed toward a lens 12 by a mirror 11. Lenses 12, 13 and 14 function together as a beam culminator to culminate light 9 into a culminated light 8. A spatial light modulator (SLM) 15 is controlled on the basis of data input by a computer 19 via a bus 18 to selectively redirect portions of light from a path 7 toward an enlarger lens 5 and onto screen 2. The SLM 15 is implemented with a mirror array comprising large number of mirror 33 each includes a deflectable reflective element shown as elements 17, 27, 37, and 47 depicted in FIG. 1B. Each mirror 33 is connected by a hinge 30 on a surface 16 of a substrate in the electromechanical mirror device as shown in FIG. 1B. When the element 17 is in one position, a portion of the light from the path 7 is redirected along a path 6 to lens 5 where it is enlarged or spread along the path 4 to impinge on the screen 2 to display an illuminated pixel 3. When the element 17 is in another position, the light is redirected away from screen 2 and hence the pixel 3 is displayed as a dark pixel on the display screen 2.
The mirror device comprises a plurality of mirror elements to function as spatial light modulator (SLM) wherein each mirror element comprises a mirror and electrodes. A voltage applied to the electrode(s) generates a coulomb force between the mirror and the electrode(s) to control the mirror to tilt to an inclined angle. According to a common term used in this specification, the mirror is “deflected” to an angular position for describing the operational condition of a mirror element.
When a voltage applied to the electrode(s) controls the mirror to deflect to a controlled angular position, the deflected mirror also reflects an incident light to a controlled direction. The direction of the reflected light is therefore controlled in accordance with the deflection angle of the mirror and that in turn is controlled by a voltage applied to the electrode. The present specification refers to a state of the mirror as an ON state when the mirror reflects substantially the entirety of an incident light a projection path designated for image display and as an OFF state when the mirror reflects the incident light to a direction away from the designated projection path for image display.
Specifically, FIG. 1C exemplifies a control circuit for controlling a mirror element according to the disclosure in the U.S. Pat. No. 5,285,407. The control circuit includes a memory cell 32. Various transistors are referred to as “M*” where “*” designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5 and M7 are p-channel transistors; while transistors M6, M8, and M9 are n-channel transistors. The capacitances C1 and C2 represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a, which is based on a typical Static Random Access switch Memory (SRAM) design. The transistor M9 connected to a Row-line receives a data signal via a Bit-line. The memory cell 32 written data is accessed when the transistor M9 which has received the ROW signal on a Word-line is turned on. The latch 32a consists of two cross-coupled inverters, i.e., M5/M6 and M7/M8, which permit two stable states, that is, a state 1 is Node A high and Node B low, and a state 2 is Node A low and Node B high.
The control circuit, as illustrated in FIG. 1C, controls the mirrors to switch between two states, and the control circuit drives the mirror to oscillate to either the ON or OFF deflected angle (or position), as shown in FIG. 1A.
The minimum intensity of light controllable to reflect from each mirror element for image display, i.e., the resolution of gray scale of image display for a digitally controlled image display apparatus, is determined by the least length of time that the mirror is controllable to be held in the ON position. The length of time that each mirror is controlled to be held in the ON position is in turn controlled by multiple bit words.
As a simple illustration, FIG. 1D shows the “binary time intervals” when controlling micromirrors with a four-bit word. As shown in FIG. 1D, the time durations have relative values of 1, 2, 4, 8, which in turn define the relative brightness for each of the four bits where “1” is the least significant bit and “8” is the most significant bit. According to the control mechanism as shown, the minimum controllable differences between gray scales for showing different levels of brightness is a represented by the “least significant bit” that maintains the micromirror at an ON position.
For example, assuming n bits of gray scales, one time frame is divided into 2n−1 equal time periods. For a 16.7-millisecond frame period and n-bit intensity values, the time period is 16.7/(2n−1) milliseconds
For controlling deflectable mirror devices, the PWM applies data to be formatted into “bit-planes”, with each bit-plane corresponding to a bit weight of the intensity of light. Thus, if the brightness of each pixel is represented by an n-bit value, each frame of data has n bit-planes. Then, each bit-plane has a 0 or 1 value for each mirror element.
When adjacent image pixels are displayed with a very coarse gray scale caused by great differences in the intensity of light, thus, artifacts are shown between these adjacent image pixels. That leads to the degradations of image quality. The image degradations are especially pronounced in the bright areas of image where there are “bigger gaps” between of the gray scales of adjacent image pixels. The artifacts are generated by technical limitations in that the digitally controlled image does not provide a sufficient number of the gray scale.
As the mirrors are controlled to operate in a state of either ON or OFF, the intensity of light of a displayed image is determined by the length of time each mirror is in the ON position. In order to increase the number of gray scales of a display, the switching speed of the ON and OFF positions for the mirror must be increased. Therefore the digital control signals need be increased to a higher number of bits. However, when the switching speed of the mirror deflection is increased, a stronger hinge for supporting the mirror is necessary to sustain the required number of switches between the ON and OFF positions for the mirror deflection. In order to drive the mirrors with a strengthened hinge, a higher voltage is required. The higher voltage may exceed twenty volts and may even be as high as thirty volts. The mirrors produced by applying the CMOS technologies are probably not appropriate for operating the mirror at such a high range of voltages, and therefore DMOS mirror devices may be required. In order to achieve a higher degree of gray scale control, more complicated production processes and larger device areas are required to produce the DMOS mirror. Conventional mirror controls are therefore faced with a technical problem in that accuracy of gray scales and range of the operable voltage have to be sacrificed for the benefits of a smaller image display apparatus.
Furthermore, a mirror device is commonly produced by applying a process typically applied to the production process of a semiconductor. An etchant such as hydrogen fluoride or a similar etchant is used in the process. In the production process of a mirror device, a desired structure is eventually obtained by using different materials for multiple structural layers by applying different etching process using the aforementioned etchant. An unnecessary region or a sacrifice layer is removed. A protective layer (i.e., an etch-stop layer) is used to protect a part manufactured as a structural layer. Therefore, in the production process of the mirror device is carried out by selecting the material of the structural layer, the material of an inter-layer insulation film for securing the insulation between individual layers the material of a sacrifice layer, and selecting an etchant for carrying out the manufacturing processes. There are however situations the etchant may migrate from an obscure gap between individual layers cause an area originally not design for exposure to the etchant inadvertently invaded by the etchant. The manufacturing processes thus cause an undesirable electrical shorting and a collapsed structural layer.
In the meantime, there are reference materials related to the present invention proposal.
U.S. Pat. No. 6,744,550 has disclosed a layered electrode having a step.
U.S. Pat. No. 6,552,840 has disclosed an electrode having a step or a slope surface.
U.S. Pat. No. 5,673,139 has disclosed a vertical silicon hinge.
U.S. Pat. No. 6,128,121 has disclosed a configuration in which electrodes are respectively placed on both sides of a vertical silicon hinge.
U.S. Pat. No. 7,068,417 has disclosed a configuration in which electrodes are respectively placed on both sides of a vertical silicon hinge.
U.S. Pat. No. 7,022,249 has disclosed a configuration in which a drive electrode and a mirror abut on each other.
U.S. Pat. No. 6,735,008 has disclosed a structure in which electrodes, each of which is constituted by an insulation layer and an electric conductor, are respectively placed on both sides of a vertical hinge.
U.S. Pat. No. 5,447,600 has discloses an electrode, on which a mirror abuts, and a drive electrode.
U.S. Pat. No. 6,914,709 has disclosed the structure of an electrode of a mirror.
U.S. Pat. No. 7,079,301 has disclosed the structure of an electrode of a mirror.
U.S. Pat. No. 6,912,336 has disclosed a metal-deposited electrode.
U.S. Pat. No. 6,962,419 has disclosed an electrode having different heights depending on the deflecting direction of a mirror.
U.S. Pat. No. 7,206,110 has disclosed a configuration using a metallic layer for shielding light.
U.S. Pat. No. 5,818,095 has disclosed a configuration using a metallic layer for shielding light.
However, these disclosures have not yet provided an effective configuration and method to overcome the technical limitations encountered in the conventional image display systems. Therefore, a need still exists in the art of image display systems applying digital control of a mirror array as a spatial light modulator to provide new and improved systems such that the above-discussed difficulties can be resolved.